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RISC-V Summit: SiFive’s 4th generation embedded cores

By June 25, 2024June 26th, 2024No Comments

SiFive announced the 4th generation of RISC-V CPU cores for embedded applications at RISC-V Summit Europe 2024 today.

There are eight cores, three of which are 32bit while the other five are 64bit.

To trade performance against power and area, their pipelines will span two-stage single-issue, to eight-stage dual-issue – see the table below.

They are all covered by the companies ‘Essential’ range branding, and SiFive is claiming “up op 40% runtime power reduction” compared with its third generation Essential processors.

Read the article here.

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