By Rick O’Connor, Executive Director of the RISC-V Foundation
With more than 1,100 attendees from over 20 countries, the RISC-V Summit in Santa Clara was a true testament of the growth of the RISC-V ecosystem over the past year. More than double the size of the 7th RISC-V Workshop in Milpitas, the inaugural RISC-V Summit featured more than 50 presentations and 29 exhibitors discussing RISC-V implementations and how the RISC-V ISA will shape the industry for decades to come.
Throughout the event, sessions tackled hot topics around compliance, edge computing, embedded development, the Internet of Things, machine learning, memory, storage/data and – one of the most fundamental issues of our connected world – security. Check out the videos and presentations from the RISC-V Summit on our proceedings page.
Below is a video showcasing RISC-V Summit:
We were thrilled to have industry luminaries deliver keynotes, including:
- Michael Gielda, VP Business Development at Antmicro (Slides & Video)
- Robert Shearer, Director of Silicon Architecture and Modeling at Facebook
- Patrick Johnson, Vice President, Mixed Signal and FPGA Business Units at Microchip Technology (Slides & Video)
- Rob Oshana, VP Software Engineering at NXP (Slides & Video)
- Greg Wright, Sr. Director, Engineering at Qualcomm (Slides & Video)
- David Patterson, Vice Chair of the Board at the RISC-V Foundation (Slides & Video)
- Yunsup Lee, CTO at SiFive (Video)
- Krste Asanovic, professor at UC Berkeley and Chief Architect at SiFive (Slides & Video)
- Martin Fink, Executive Vice President and Chief Technology Officer at Western Digital (Slides & Video)
Keynote by David Patterson, Vice Chair of the Board at the RISC-V Foundation and 2017 ACM A.M. Turing Award winner
The event also included a lively keynote panel on security (Video) moderated by Ed Sperling, Editor In Chief at Semiconductor Engineering, with panelists: Helena Handschuh, Chair of the RISC-V Foundation Security Standing Committee and Fellow at Rambus; Joseph Kiniry Principal Scientist at Galois; and Richard Newell Senior Principal Product Architect at Microsemi, a subsidiary of Microchip Technology.
Panel on Opportunities and Challenges in Security for Open Source Hardware
Amid the companies showcasing their latest innovations in the exhibit hall, participants in the RISC-V Linux Hackathon battled it out to create cutting edge applications on a soft RISC-V CPU running Linux on the low-cost Avalanche FPGA board.
RISC-V Linux Hackathon
We also celebrated the winners of the RISC-V SoftCPU Contest for creating innovative FPGA based CPU implementations targeting the RISC-V ISA, and honored Daniel Lustig, Chairman Of The RISC-V Memory Model Task Group and renowned research scientist at NVIDIA Corporation, with the inaugural RISC-V Foundation Board of Directors’ Award.
Of course, there were happy hours and parties too! Ashling sponsored the happy hour on the first and second days of the event, and Western Digital and SiFive hosted a lively Innovation Celebration.
A special guest at Western Digital and SiFive’s Innovation Celebration
Check out a recap of news from the RISC-V Summit:
- Andes Technology: Andes Custom Extension™ Further Accelerates Your High Performance RISC-V Processors
- Antmicro: Renode 1.6 Released Making Linux-Enabled RISC-V Microchip PolarFire SoC Available To Everyone
- Codasip: Codasip Secures $10M In Series A Financing To Expand RISC-V Processor Technology Offerings
- Esperanto Technologies: Valtrix STING DV Platform Selected By AI Chipmaker Esperanto Technologies
- Imperas: Imperas Expands Commercial Operations With Quantum Leap Sales For US Market Growth
- Imperas: Imperas and Valtrix Announce Partnership for RISC-V Processor Verification
- Microchip Technology: Industry’s First RISC-V SoC FPGA Architecture Brings Real-Time To Linux, Giving Developers The Freedom To Innovate In Low-Power, Secure And Reliable Designs
- RISC-V Foundation: Daniel Lustig, Chairman Of The RISC-V Memory Model Task Group, Receives Inaugural 2018 RISC-V Foundation Board Of Directors’ Award At The RISC-V Summit
- RISC-V Foundation: RISC-V SoftCPU Contest Winners Demonstrate Cutting-Edge RISC-V Implementations For FPGAs
- SiFive: SiFive Announces Multiple Technical Advances At RISC-V Summit
- Western Digital: Western Digital Delivers New Innovations To Drive Open Standard Interfaces And RISC-V Processor Development
A special thanks to the RISC-V Summit sponsors
Although the RISC-V Summit has ended, one thing is for certain – our ecosystem continues to grow and adoption is in full swing. We are excited to reconvene next year for an even bigger and better event. Mark your calendars for RISC-V Summit 2019, taking place Dec. 3-6, 2019 at the San Jose Convention Center.
In the meantime, check out the upcoming RISC-V ecosystem events. The RISC-V Foundation will be exhibiting at Embedded World, and are hosting RISC-V Workshop Taiwan (March 12-14, 2019) and RISC-V Workshop Zurich (June 11-13, 2019). There are also a number of events hosted by RISC-V Foundation members, along with RISC-V ecosystem meetups, happening around the world.
Thanks again to all and happy holidays!