SiFive Joins Microsemi’s New Mi-V Ecosystem To Accelerate Adoption Of RISC-V Open Instruction Set Architecture

Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced SiFive, the first fabless provider of customized, open-source-enabled semiconductors, has joined Microsemi’s new Mi-V™ RISC-V ecosystem, further building out the growing ecosystem and expanding the number of RISC-V designs users can consider. Microsemi will leverage its strategic relationship with SiFive and other ecosystem participants to increase adoption of RISC-V open instruction set architecture (ISA) central processing units (CPUs)…

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The Register Article: WDC To Move All Its Stuff To RISC-V Processors, Build Some Kind Of Super Data-Wrangling Stack

Western Digital has grandly announced its will use the open-source RISC-V processor architecture in all future products and “intends to lead the industry transition toward open, purpose-built compute architectures to meet the increasingly diverse application needs of a data-centric world.”To read more, please visit: https://www.theregister.co.uk/2017/12/01/wdc_risc_v_edge_strategy/

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Tom’s Hardware Article: Big Tech Players Start To Adopt The RISC-V Chip Architecture

RISC-V (pronounced risc-five) is a brand-new instruction set architecture (ISA) that’s open to customize and free to use by anyone. The ISA is only a few years old, but both large and small companies, such as Nvidia, Western Digital, and Esperanto, are now planning to use RISC-V chips to power their products.To read more, please visit: http://www.tomshardware.com/news/big-tech-players-risc-v-architecture,36011.html

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Why not build on OpenRISC?

We’ve just returned from a great meeting at the OpenRISC Conference at TU Munich. Thanks to everyone there for a thoroughly stimulating and enjoyable workshop. We hear the videos and slides will soon be posted online.A question we were often asked there, and previously in blog postings and emails, is why we didn’t just build on the OpenRISC project? We were very aware of OpenRISC and carefully studied the ISA in 2010 before deciding not…

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About our Dhrystone benchmarking methodology

This is an extended version of Krste’s comment on the RISC-V EE Times article about our Dhrystone benchmarking methodology.We have reported a Dhrystone score of 1.72 DMIPS/MHz for the Rocket core here. We pulled the Dhrystone comparison together quickly, as we kept getting asked about how we compared to ARM cores and these were the only publicly available numbers we could easily compare against. We didn’t spent a lot of time…

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