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Semiconductor Engineering Article: Why IP Quality Is So Difficult To Determine

By May 30, 2019May 12th, 2021No Comments

In many cases, IP is poorly characterized, regardless of whether that IP was commercially or internally developed by a chipmaker. But as chips become more complex, subject to more interactions from multiple power domains and use cases, even the best intentions to characterize IP can go awry.
IP quality stretches all the way to the RTL code.
“Customers want to make sure they can read RTL easily, that it can be easily followed, that it is well commented, that it synthesizes without warnings or errors, and that it is well-structured Verilog,” said Chris Jones, vice president of marketing at Codasip. “They also want support for various low power modes.”
This is particularly important for the RISC-V ISA, where quality concerns are popping up given that every physical implementation of RISC-V ISA is different. “RISC-V is merely an ISA spec, and it’s up to each provider to implement that ISA spec as they see fit,” Jones said. “The quality of RTL deliverables varies widely within the RISC-V community. Part of that is expected because part of these are academic contributed cores with limited support. But even a recently announced core that the developer [a fabless semiconductor company] patted itself on the back for open sourcing has a bug in the AXI bus.”
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