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NOEL-V: A RISC-V Processor for High-Performance Space Applications

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Space applications pose significant challenges for electronic systems as they must contend with a myriad of environmental factors once they are launched. These factors include extreme temperatures, radiation, shock, and…

RISC-V: An Open Standard Instruction Set Architecture

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By Mark Himelstein, CTO of RISC-V International In this blog post, we’ll explain why RISC-V is an open standard instruction set architecture (ISA). We’ve received some questions about whether RISC-V…

In the News

Axelera AI increases its Series A funding round to $50m for RISC-V edge AI chip

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Dutch startup Axelera AI has raised $50m for its in-memory computing, RISC-V-based edge AI technology and set up a Silicon Valley office. CDP Venture Capital, Verve Ventures and Fractionelera have…

SiFive Gives WorldGuard to RISC-V International to Make this Robust Security Model More Accessible to the RISC-V Community

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SANTA CLARA, Calif.--(BUSINESS WIRE)--SiFive, Inc., the pioneer and leader of RISC-V computing, today announced the company is giving the WorldGuard security model to RISC-V International, providing the RISC-V community with…


Ashling and Imagination announce Ashling’s RiscFree™ C/C++ SDK support for RISC-V-based Catapult family.

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Embedded World, Mar-14 2023, Nuremberg, Germany. Ashling and Imagination Technologies announced today that Ashling’s RiscFree SDK will provide software development  support for Imagination’s Catapult RISC-V-based IP cores.   RTXM-2200 is the…

First-ever RISC-V Summit Europe Will Demonstrate Technical and Commercial Momentum Across Industries

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The Barcelona RISC-V Summit from June 5-9 to focus on industries such as Automotive, High Performance Compute/Data Center, and Security; Call for Submissions and Sponsorships now open   BARCELONA, Spain…

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