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EDN: The next RISC-V processor frontier: AI

EDN: At RISC-V Summit North America 2025, industry leaders unveiled the latest advances in CPU cores, vector processors, and AI-powered designs shaping the next wave…

Upbeat Technology
All About Circuits: Upbeat Technology’s RISC-V MCU Takes Flight With Near-Threshold Computing

Developed with SiFive, the dual-core SoC uses patented error correction to achieve a record 16.8 µW/MHz/DMIPS, targeting next-gen wearables, drones, and IoT sensors. In a…

EETimes
EETimes: Google Open-Sources NPU IP, Synaptics Implements It

Google Research has open-sourced its Coral NPU IP (previously codenamed Kelvin), which it is giving to the industry in a bid to accelerate edge AI…

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The RISC-V instruction set architecture (ISA) offers a highly customizable open standard platform, enabling developers to build, port, and optimize software applications, extensions, and hardware. Its simplicity and modularity enables efficient design and optimization, fostering innovation and reducing development time and cost.

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Becoming a member of RISC-V International allows companies to actively influence the development of an open, royalty-free instruction set architecture, driving innovation in custom processor designs. Membership also provides access to a global community of experts and resources, fostering collaboration and accelerating product development.

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RISC-V Fundamentals + Foundational Associate Exam Bundle

Designed for computer engineers and programmers to gain skills in RISC-V processors, enhancing your job market competitiveness. Essential learning experience for anyone looking to enhance their career in the tech industry.

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