6th RISC-V Workshop Proceedings
Shanghai, China May 8-11, 2017
This workshop was a four day event broken down as follow:
- Monday May 8, 2017 – Introduction to RISC-V – this day long session was held for those who were new to RISC-V and have yet to be exposed to the RISC-V ISA. The session consisted of presentations from the RISC-V Foundation, some of the original creators of the RISC-V ISA and product presentations from vendors within the RISC-V community.
- Tuesday and Wednesday May 9-10, 2017 – These two days followed our traditional two day format with presentations covering various RISC-V projects underway within the RISC-V community and will included a poster / demo reception on Tuesday evening.
- Thursday May 11, 2017 – The workshop week concluded with RISC-V Foundation meetings with attendance restricted to members of the RISC-V Foundation. The day consisted of Technical and Marketing Committee face to face meetings to progress the work currently underway within our various Task Groups.
Each workshop has helped both document the rapidly rising popularity of RISC-V and boosted it further due to the information shared and collaborations formed at the event.
The 7th RISC-V workshop will be hosted by Western Digital in Milpitas California the week of November 27th, 2017. Save the date and please join us! Registration details and the Call for Papers will be posted later this summer.
6th Workshop Agenda & Proceedings
Monday, May 8th, 2017 Introduction To RISC-V
| Time | Event | Speaker, Affiliation | Media |
| 8:00am | Registration and Networking Breakfast | ||
| 9:00am | RISC-V Introduction – Opening Remarks | Rick O’Connor, Executive Director, RISC-V Foundation; Professor Zhigang Mao, Department of Micro/Nano Electronics, Shanghai Jiao Tong University | Video |
| 9:15am | History of Computer Architecture and RISC | Dave Patterson, Pardee Professor of Computer Science, Emeritus, UC Berkeley and author of “Computer Architecture: A Quantitative Approach” | Slides | Video |
| 10:15am | Networking Break | ||
| 10:45am | Why RISC-V? “Instruction Sets Want to be Free” | Krste Asanovic, Professor UC Berkeley, Chairman RISC-V Foundation, Co-Founder SiFive | Slides | Video |
| 11:45am | Introduction to the RISC-V Foundation | Rick O’Connor, Executive Director, RISC-V Foundation | Slides | Video |
| 12:15pm | Morning Session Wrap UP | Rick O’Connor, Executive Director, RISC-V Foundation | |
| 12:30pm | Networking Lunch | ||
| 1:30pm | RISC-V Member Company Introductions | Various RISC-V Foundation Member Companies | Slides | Video |
| 2:15pm | RISC-V Foundation Mini Trade Show | Various RISC-V Foundation Member Companies | |
| 5:00pm | Adjourn for the Day |
Tuesday, May 9th, 2017 6th RISC-V Workshop Day 1
| Time | Event | Speaker, Affiliation | Media |
| 8:00am | Registration and Networking Breakfast | ||
| 8:45am | 6th RISC-V Workshop Introduction | Rick O’Connor, RISC-V Foundation | Slides | Video |
| 9:00am | Taking RISC-V to Mainstream ASICs | Charlie Su, Andes Technology | Slides | Video |
| 9:30am | Labeled RISC-V: A New Perspective on Software-Defined Architecture | Zihao Yu, ICT Chinese Academy of Sciences | Slides | Video |
| 10:00am | RISC-V Privileged Architecture | Andrew Waterman, SiFive | Slides | Video |
| 10:30am | Networking Break | ||
| 11:00am | RISC-V Foundation Update | Rick O’Connor, RISC-V Foundation | Slides | Video |
| 11:15am | RISC-V Technical Committee Update | Yunsup Lee, SiFive | Slides | Video |
| 11:30am | RISC-V Marketing Committee Update | Jack Kang, SiFive | Slides | Video |
| 11:45am | Panel Discussion: RISC-V in China | Video | |
| 12:30pm | Networking Lunch | ||
| 1:45pm | Keynote Address: RISC-V at NVIDIA | Frans Sijstermans, NVIDIA | Slides | Video |
| 2:30pm | SCR1 – open-source RISC-V compatible MCU core with support | Ekaterina Berezina, Syntacore | Slides | Video |
| 2:45pm | Making RISC-V IP easy to play with and evaluate | Jack Kang, SiFive | Slides | Video |
| 3:00pm | Automated RISC-V Verification Flow Utilizing Simulation, Formal, and Emulation Technologies | Marcela Zachariasova, Codasip | Slides | Video |
| 3:30pm | Networking Break | ||
| 4:00pm | Reprogrammable Logic in a RISC-V based SoC | Alok Sanghavi, Achronix | Slides | Video |
| 4:30pm | A RISC-V Instruction-set extension for baseband processing applications | Cecil Accetti, Shanghai Jiao Tong University | Slides | Video |
| 4:45pm | Poster / Demo Previews ~ 2min per presenter | Slides | Video | |
| 5:15pm | Transition to Reception | ||
| 5:30pm | Networking Reception, Posters Sessions and Demos | ||
| 9:00pm | Adjourn for the Day |
Wednesday, May 10th, 2017 6th RISC-V Workshop Day 2
| Time | Event | Speaker, Affiliation | Media |
| 8:00am | Networking Breakfast | ||
| 9:00am | Dual-core Lockstep Processor using RISC-V Softcores | Sathish Odiga, Microsemi | Slides | Video |
| 9:30am | The 4th lowRISC release: Tagged memory and minion cores | Wei Song, University of Cambridge / lowRISC | Slides | Video |
| 10:00am | Status of the RISC-V Memory Consistency Model | Daniel Lustig, NVIDIA | Slides | Video |
| 10:30am | Networking Break | ||
| 11:00am | Keynote Address: Impedance Matching Expectations Between RISC-V and the Open Hardware Community | Bunnie Huang | Slides | Video |
| 12:00pm | Networking Lunch | ||
| 1:30pm | Panel Discussion: RISC-V Ask Me Anything | Video | |
| 2:15pm | Modern Software Development Methodology for RISC-V Devices | Larry Lapides, Imperas | Slides | Video |
| 2:45pm | RISC-V Debug Updates | Megan Wachs, SiFive | Slides | Video |
| 3:15pm | Networking Break | ||
| 3:45pm | RISC-V Hardware Accelerated Dynamic Binary Translation | Simon Rokicki, IRISA | Slides | Video |
| 4:15pm | 28 Microwatt RV32IMAC | Lauri Koskinen, Minima Processor | Slides | Video |
| 4:30pm | 6th RISC-V Workshop Conclusion | Rick O’Connor, RISC-V Foundation | Video |
| 4:45pm | End of Workshop |